An engineering team's checklist for the six manufa
The questions we ask before a board hits routing — stackup, panelisation, fiducials, testpoint access — and why front-loading them collapses the iteration cycle.
Differential pair geometry, reference plane choice, and the impedance tolerances we hold to keep eye diagrams clean above 16 GT/s.
Power-plane filtering, return-path discipline, and the four PCB-level interventions that have saved our customers a second trip to the EMC chamber.
How to size bulk and high-frequency decoupling on a 12-rail SoC without blindly stamping 100 caps near the package, plus the Z-parameter targets we measure against.
Why the 3W rule isn't enough at 3200 MT/s, and how we allocate near-end and far-end crosstalk budgets across address, command, and data groups.
A measured study from our thermal lab: ground-plane area, via stitch density, and how much each one buys you in junction temperature at 5A continuous.
Bend radius math, copper thickness selection, and the coverlay decisions that separate a board that lives 6 months in a hinge from one that lasts a decade.
The break-even analysis we run before recommending HDI: pitch, escape routing density, and the layer-count savings that make stacked microvias cheaper than a 12-layer alternative.
Sheet organisation conventions, signal naming, and the page-flow patterns that turn a 40-sheet schematic from a maze into a manual.