The PCB Design Handbook: What Every Hardware Team Should Validate Before First Spin

Most spins we see could have been avoided with a 20-minute call about stackup before routing started. Layer count, dielectric choice, and impedance reference planes cascade into everything: trace widths, BGA escape strategy, power integrity headroom, and ultimately the unit-cost tier you'll quote.

Here are the four numbers we ask for on every first engagement:

• Layer count — driven by escape routing from the densest BGA, not by overall complexity. A single 0.5mm-pitch BGA with 200+ signals will push you to 8 layers even on a "simple" board.
• Total stackup thickness — typically 1.6mm, but card-edge connectors, press-fit pins, and certain shielding cans force this.
• Copper weight — 1oz outers is default; bump to 2oz only if you're pushing >3A continuously on a power plane.
• Material — standard FR-4 (Tg 150°C) covers most cases. Reach for Tg 170+ when reflow profile peak exceeds 245°C or when ambient field temperature passes 85°C.

"The fastest way to make a board cheaper is to delete a layer. The fastest way to make it unmanufacturable is to delete the wrong one." — Pioneer Horizon DFM lead

Controlled impedance is one of the few things on a board that's cheaper to get right in CAD than to fix after fab. Trace width and dielectric height interact non-linearly — copy-pasting widths from a different stackup is the single most common cause of impedance failure we see at IFI.

Single-ended targets we hold to

• 50Ω ±10% for general high-speed (USB 3.x SS lanes, DDR address/command).
• 40Ω ±10% for legacy DDR2 reference.
• 75Ω ±10% for video / coax-equivalent traces.

Differential pairs

• 85Ω ±10% — USB 2.0 differential.
• 90Ω ±10% — USB 3.x SuperSpeed.
• 100Ω ±10% — Ethernet, LVDS, PCIe up to Gen3.
• 100Ω ±7% — PCIe Gen4 and above (the tighter tolerance is non-negotiable).

Hand these targets to your fab on the stackup drawing. We provide impedance test coupons on every panel and ship the report with the lot — no separate request needed.

Most DFM violations are cosmetic. A handful materially affect yield. Here are the ones we flag first in every review:

1. Annular ring minimums on inner layers

If your via drill is 0.3mm and the pad is 0.55mm, you have 0.125mm of annular ring per side — minus the inner-layer registration tolerance of typically 0.075mm, you're at 0.05mm of guaranteed copper. That's below the 0.075mm minimum for IPC-A-600 Class 2. Bump the pad to 0.6mm.

2. Solder mask sliver between pads

Solder mask between two SMD pads less than 0.1mm wide will tear off in production. The mask isn't optional decoration — it stops bridging. If the gap is <0.1mm, the mask manufacturer will skip it and you'll get bridging on the line.

3. Acid traps

Acute internal angles in copper (less than ~70°) hold etchant during processing and produce undercut traces. Soften with a small fillet or 45° break. Most modern CAD tools will flag these in DRC if you turn the rule on.

4. Plane splits under high-speed traces

A return current that has to detour around a plane split sees a sharp impedance discontinuity. For DDR or SerDes signals, this often shows up as a single failing channel that "passes signal integrity simulation but fails compliance test." Stitch the planes with caps, or move the trace.

For a deeper walk-through, see our 20-minute DFM review process — that's the call we run before any board gets layout time.

The cheapest power-integrity fix is a stackup change. The next-cheapest is decoupling network design. The most expensive is rework after thermal runaway in the field. We run these checks before routing starts:

1. Rail map — every rail listed with: voltage, max current, transient slew, ripple budget, and decoupling target impedance across DC–100MHz.
2. Plane area per rail — minimum 4 sq cm per amp continuous for 1oz copper. Below that, you're stacking thermal risk.
3. Decoupling cap placement — high-frequency caps (0.1µF, 0.01µF) within 5mm of the load BGA; bulk caps (1–10µF) at the rail entry; plane capacitance for the >100MHz range.
4. Return path discipline — every high-speed signal has a continuous reference plane on the layer immediately adjacent. No exceptions on SerDes.

If you skip this and find out at EVT, expect a second spin. We catch about 70% of PI problems in this pre-route review — the remaining 30% emerge from real measurements on the prototype.

Panelisation looks like a fab concern but it shows up on your unit cost line. A panel that yields 12 boards instead of 10 is a 20% cost reduction at the same panel price. Two rules:

• Match the fab's standard panel — typically 18"×24" or 21"×24" in this region. Designing to fit cleanly inside one of those, accounting for V-groove + tooling rails, often unlocks the next yield tier.
• Don't fight the SMT line — minimum 3mm rail on the long side for conveyor clamping. Without it, panels run on carriers and you pay the carrier amortisation per build.

Fiducials we expect

• Three global fiducials per panel — diagonal triangle, not collinear.
• Two local fiducials per board for any BGA with pitch < 0.65mm.
• 1mm circle, 2mm clearance ring, on the same layer as the components they reference.

A panel without proper fiducials runs at reduced placement speed (the machine slows to vision-align each board), so you pay for it twice: once in setup time, once in cycle time.

Before you send Gerbers, we run a structured checklist. Ten items, ten minutes per item. The cost of going through it is one engineer-day. The cost of skipping it is, on average, one re-spin — call it $8–15k of board + assembly + lost calendar time.

1. Stackup matches impedance targets (verified against fab's actual lamination).
2. All rails decoupled to plan, with caps placed and routed.
3. DRC clean against fab's actual capability file, not the generic one.
4. BOM passes — every line has an active part with stock, plus an approved alternate.
5. Footprint library cross-checked against datasheets — pin 1 markers, polarity indicators.
6. Mechanical alignment to enclosure CAD (mounting holes, connector positions, height clearances).
7. Silk legible — no overlapping refs, no silk on pads, mil-thick lines.
8. Test points defined — minimum coverage for ICT, named net by net.
9. Fiducials placed and labelled.
10. Panel drawing reviewed by fab before tapeout.

We do this checklist with our customers' design teams as a complimentary first-engagement service — the half-day we invest catches more than it costs us, every time.

Ready to walk through this on your design? Send us your Gerbers — we'll come back within two working days with a manufacturability report and a quote.