PCB Design & Engineering

Schematic capture, multilayer layout, signal integrity, and DFM under one accountable team. Designs that route on the first spin and assemble cleanly on our SMT lines.

  • Multilayer PCB Design
  • High-Speed Routing
  • RF & Power Electronics Layout
  • Impedance Control
  • EMI/EMC Optimization
  • Design for Manufacturability (DFM)
Structured Manufacturing Workflow

From design to delivery, six audited gates.

Design → DFM → SMT → Inspection → Testing → Delivery. Each transition is documented, inspected, and signed off — so the board you ordered is the board that ships.

1

Design

Schematic + multilayer layout against your spec, with stackup and impedance targets locked.

2

DFM

10-point pre-tapeout review against our fab's actual capability file. Iteration loop here saves a spin.

3

SMT

Lines 1–4 at Madurai, fine-pitch BGA and 0201 placement at 80k CPH with paste verification.

4

Inspection

100% AOI on top and bottom, X-ray on BGA voids, plus IPC-A-610 visual sign-off.

5

Testing

ICT for high-volume, flying probe for low-volume, plus functional test against your firmware.

6

Delivery

ESD-safe packaging, MBB + desiccant for export, full traceability pack with every shipment.

Capability detail

Six practices that decide whether your board routes on the first spin.

Each capability is a discipline our design team runs to its own checklist — with specific limits and tolerances you can hand to your customer's audit team.

01

Multilayer PCB Design

From 2-layer single-sided boards to 16-layer high-density stackups with controlled impedance — sized to your escape routing, signal speed, and cost targets.

Layer count2 – 16 layers
Min trace / spacing3 mil / 3 mil
Stackup materialFR-4 Tg 150 – 170
02

High-Speed Routing

DDR4/5, PCIe Gen4/5, USB 3.x SS and Ethernet routed against measured impedance targets with controlled differential pairs and disciplined return paths.

Diff impedance85 / 90 / 100 Ω ±10%
Tested atUp to 16 GT/s
Reference planeContinuous, adjacent
03

RF & Power Electronics

RF microstrip / stripline for sub-6 GHz and mmWave; tight power layout for DC-DC converters and IGBT/MOSFET stages with snubber and gate-drive isolation.

RF rangeDC – 28 GHz
PowerUp to 1000 V isolated
TopologyBuck, boost, flyback, LLC
04

Impedance Control

Stackup-aware impedance design with per-panel test coupons. Documented impedance reports ship with every prototype lot.

Single-ended50 Ω ±10%
Differential85 / 90 / 100 Ω ±7–10%
CouponsPer panel + per lot
05

EMI/EMC Optimization

Plane decoupling, return-path discipline, and ground-stitching strategy refined for pre-compliance success. Saves the second trip to the EMC chamber.

StandardsEN 55032, CISPR 32, FCC Part 15
Pre-complianceNear-field probe scan
Filter designπ / T LC stages
06

Design for Manufacturability

Every design passes our 10-point DFM review before tapeout: annular ring, courtyard, panelisation, fiducials, testpoint coverage, mask slivers, plane splits.

DFM checklist10-point gate
Panel utilisationTarget ≥ 85%
Test coverageICT + FCT ready
Technical specifications

The numbers we routinely run, not the ceiling.

These thresholds describe the design window we'll quote against without question. Tighter targets are possible — ask, and we'll let you know what changes.

SpecificationValue
Layer count2 – 16 layers
Min trace / spacing3 mil / 3 mil
Min via0.15 mm drill, 0.30 mm pad
BGA pitch0.4 mm and above
Annular ring (inner)≥ 0.075 mm (IPC Class 3)
Controlled impedance±10% (±7% for PCIe Gen4+)
MaterialFR-4 Tg 150 / 170, polyimide for rigid-flex
Copper weight1 oz / 2 oz outer · 0.5 / 1 oz inner
Surface finishENIG, HASL, OSP, immersion silver
Standard turnaroundLayout: 5–10 days · Prototype: 7–14 days
CAD & simulation stack

Tooling that your team probably already uses.

We accept native project files from the major EDA suites and sign-off simulators — no format-conversion gymnastics, no "please re-export as Gerber."

Altium DesignerCadence AllegroKiCadMentor XpeditionHyperLynx SI/PIPolar SI9000Ansys SIwaveSaturn PCB ToolkitValor NPICAM350
Engineering notes

Read what our design team actually writes about.

Selected articles from the PCB Design & Engineering corpus — DFM, impedance, signal integrity, and the calls we make before tapeout.

Browse all PCB Design articles
Questions, answered

PCB design, answered.

What hardware teams ask before handing us a schematic — answered against our real layout capability.

How many layers can you design?

From 2-layer single-sided boards to 16-layer high-density stackups with controlled impedance, on FR-4 Tg 150–170 or polyimide for rigid-flex — sized to your escape routing, signal speed, and cost target.

Do you design high-speed boards like DDR4/5 and PCIe Gen4/5?

Yes. We route DDR4/5, PCIe Gen4/5, USB 3.x SuperSpeed, and Ethernet against measured impedance targets (85/90/100 Ω differential) with continuous reference planes, validated up to 16 GT/s.

Which PCB design tools and file formats do you work in?

Altium Designer, Cadence Allegro, KiCad, and Mentor Xpedition, with HyperLynx and Ansys SIwave for SI/PI. We accept native project files or a full Gerber/ODB++ package.

What is the typical turnaround for a PCB layout?

Layout runs 5–10 working days and a built prototype 7–14 days, depending on layer count and complexity. Every design clears a 10-point DFM gate before tapeout to avoid a re-spin.

Do you provide controlled-impedance test reports?

Yes. Stackups are designed impedance-aware with per-panel test coupons, and a documented impedance report ships with every prototype lot — single-ended 50 Ω and differential 85/90/100 Ω to ±7–10%.

Can you take the design straight through to manufacturing?

Yes — design, SMT assembly, and test are all in-house, so a board moves from layout to our Madurai line without handing off to a separate fab, and the DFM review is written against the line that will actually build it.

Let's get to work

Have a board in CAD or napkin sketch?

Send what you have — schematic, BOM, mechanical drawing, or just a target spec — and we'll come back within two working days with a manufacturability review and a quote.

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