Multilayer PCB Design
From 2-layer single-sided boards to 16-layer high-density stackups with controlled impedance — sized to your escape routing, signal speed, and cost targets.
Schematic capture, multilayer layout, signal integrity, and DFM under one accountable team. Designs that route on the first spin and assemble cleanly on our SMT lines.
Design → DFM → SMT → Inspection → Testing → Delivery. Each transition is documented, inspected, and signed off — so the board you ordered is the board that ships.
Schematic + multilayer layout against your spec, with stackup and impedance targets locked.
10-point pre-tapeout review against our fab's actual capability file. Iteration loop here saves a spin.
Lines 1–4 at Madurai, fine-pitch BGA and 0201 placement at 80k CPH with paste verification.
100% AOI on top and bottom, X-ray on BGA voids, plus IPC-A-610 visual sign-off.
ICT for high-volume, flying probe for low-volume, plus functional test against your firmware.
ESD-safe packaging, MBB + desiccant for export, full traceability pack with every shipment.
Each capability is a discipline our design team runs to its own checklist — with specific limits and tolerances you can hand to your customer's audit team.
From 2-layer single-sided boards to 16-layer high-density stackups with controlled impedance — sized to your escape routing, signal speed, and cost targets.
DDR4/5, PCIe Gen4/5, USB 3.x SS and Ethernet routed against measured impedance targets with controlled differential pairs and disciplined return paths.
RF microstrip / stripline for sub-6 GHz and mmWave; tight power layout for DC-DC converters and IGBT/MOSFET stages with snubber and gate-drive isolation.
Stackup-aware impedance design with per-panel test coupons. Documented impedance reports ship with every prototype lot.
Plane decoupling, return-path discipline, and ground-stitching strategy refined for pre-compliance success. Saves the second trip to the EMC chamber.
Every design passes our 10-point DFM review before tapeout: annular ring, courtyard, panelisation, fiducials, testpoint coverage, mask slivers, plane splits.
These thresholds describe the design window we'll quote against without question. Tighter targets are possible — ask, and we'll let you know what changes.
| Specification | Value |
|---|---|
| Layer count | 2 – 16 layers |
| Min trace / spacing | 3 mil / 3 mil |
| Min via | 0.15 mm drill, 0.30 mm pad |
| BGA pitch | 0.4 mm and above |
| Annular ring (inner) | ≥ 0.075 mm (IPC Class 3) |
| Controlled impedance | ±10% (±7% for PCIe Gen4+) |
| Material | FR-4 Tg 150 / 170, polyimide for rigid-flex |
| Copper weight | 1 oz / 2 oz outer · 0.5 / 1 oz inner |
| Surface finish | ENIG, HASL, OSP, immersion silver |
| Standard turnaround | Layout: 5–10 days · Prototype: 7–14 days |
We accept native project files from the major EDA suites and sign-off simulators — no format-conversion gymnastics, no "please re-export as Gerber."
Selected articles from the PCB Design & Engineering corpus — DFM, impedance, signal integrity, and the calls we make before tapeout.
What hardware teams ask before handing us a schematic — answered against our real layout capability.
From 2-layer single-sided boards to 16-layer high-density stackups with controlled impedance, on FR-4 Tg 150–170 or polyimide for rigid-flex — sized to your escape routing, signal speed, and cost target.
Yes. We route DDR4/5, PCIe Gen4/5, USB 3.x SuperSpeed, and Ethernet against measured impedance targets (85/90/100 Ω differential) with continuous reference planes, validated up to 16 GT/s.
Altium Designer, Cadence Allegro, KiCad, and Mentor Xpedition, with HyperLynx and Ansys SIwave for SI/PI. We accept native project files or a full Gerber/ODB++ package.
Layout runs 5–10 working days and a built prototype 7–14 days, depending on layer count and complexity. Every design clears a 10-point DFM gate before tapeout to avoid a re-spin.
Yes. Stackups are designed impedance-aware with per-panel test coupons, and a documented impedance report ships with every prototype lot — single-ended 50 Ω and differential 85/90/100 Ω to ±7–10%.
Yes — design, SMT assembly, and test are all in-house, so a board moves from layout to our Madurai line without handing off to a separate fab, and the DFM review is written against the line that will actually build it.
Send what you have — schematic, BOM, mechanical drawing, or just a target spec — and we'll come back within two working days with a manufacturability review and a quote.