PDN Design for Multi-Rail SoCs — Decoupling Math That Holds Under Load Transients

Open the power-delivery section of a modern application-processor datasheet and you'll find a table of 10–14 power rails, each with a voltage tolerance, a peak current, a transient slew rate, and — if you're lucky — a target impedance vs frequency profile. That last item is the only one that matters at layout time, and it's the one most teams treat as optional. Skip it and you'll either over-design (stamping 90 capacitors near the package "to be safe") or under-design (the board passes bring-up but fails when the GPU spools up at 70°C).

The PDN problem is fundamentally a frequency-domain problem. The SoC draws a current waveform with content from DC to several GHz. The PDN has to present an impedance below the target across that entire range, or the supply voltage will sag (at low frequency) or ring (at high frequency) and the SoC will glitch.

Where the target impedance comes from

For a rail with voltage V, ripple budget ΔV, and peak transient current I_t:

• Z_target = ΔV / I_t, held from DC to the bandwidth of the load transient.
• Example: 1.0V core rail with 50 mV ripple budget and 8A peak transient → Z_target = 6.25 mΩ.
• Bandwidth: typically 1/(π · t_rise) where t_rise is the load transient rise time. A 1 ns transient gives ~320 MHz; a 100 ps transient gives ~3.2 GHz.

"You're not picking capacitors. You're shaping an impedance curve. The capacitors are the knobs." — Pioneer Horizon PI lead

This reframe is the unlock. Once you treat the PDN as an impedance-shaping problem, the decisions become precise: which capacitor value lands its self-resonance where, how many of each value to parallel, and where on the board to place them. The next three sections walk that math.

Bulk decoupling owns the low-frequency end of the PDN impedance curve, from DC up to roughly 1 MHz. It's set by the output capacitance of the upstream regulator plus a few large electrolytics or tantalums at the board entry point.

Bulk sizing rules we hold

• Output cap of the regulator — sized per the regulator's stability requirements. A typical POL buck wants 22–47 µF of low-ESR ceramic on the output.
• Board-entry bulk — additional 100–470 µF tantalum or polymer at the point of regulation, to handle slower load steps (driver-initiated power state transitions, cold-start enumeration).
• Tolerance to capacitor de-rating — MLCCs lose 50–80% of their rated capacitance at full DC bias. Specify 2–4× the nominal value, or use polymer/tantalum where bias de-rating is unacceptable.

Mid-frequency — the 1 MHz to 100 MHz band

This is where most of the PDN action happens. The capacitors here are 0.1 µF, 1 µF, and 10 µF MLCCs, scattered across the rail's plane region. The number and placement of these caps is where over-design and under-design diverge.

1. Group capacitors by self-resonant frequency (SRF), not by value. A 0.1 µF 0402 has SRF around 30 MHz; a 1 µF 0603 around 8 MHz; a 10 µF 0805 around 2 MHz. You want the SRFs to overlap to maintain low Z across the band.
2. Parallel multiple caps of the same value rather than reaching for exotic values. Five 1 µF in parallel give five times the capacitance and a slightly higher SRF (lower combined ESL).
3. Spread them across the plane region. Bunching all the mid-frequency caps in one corner creates an impedance hotspot at the opposite corner of the rail.
4. Avoid mixing wildly different values on the same plane — anti-resonances between two capacitors with adjacent SRFs can create impedance peaks higher than either cap alone.

For a typical 1A SoC rail, we end up with roughly 8–14 mid-frequency caps, spread across the plane, after simulation. A naive design might stamp 30. The right design is the one that hits the Z-target curve, not the one with the most components.

Above ~100 MHz, individual capacitors stop helping much. Their ESL (the via inductance and the package inductance) dominates the impedance, and the via from the cap pad to the plane behaves like a small inductor — typically 0.3–0.7 nH per via, which presents 0.2–0.4Ω at 100 MHz and 2–4Ω at 1 GHz.

What actually controls the >100 MHz range

• Plane capacitance — the power plane and the adjacent ground plane form a distributed parallel-plate capacitor. With a 3 mil dielectric, FR-4 plane capacitance is roughly 600 pF/inch² of plane area. That distributed capacitance is fast — it doesn't depend on via inductance.
• Package decoupling — caps integrated into the SoC package (LSCs in some processors, embedded planes in others) handle the GHz-band. You don't get to redesign the package; you get to choose a part that has them or doesn't.
• BGA via field design — how the rail's vias are arranged in the BGA breakout determines the parasitic inductance from plane to die. Tighter arrangements with more parallel vias mean lower inductance.

Layout patterns we hold

1. Thin power/ground dielectric on rails with >500 MHz content. A 3 mil core in the stackup, dedicated to the noisiest rail, buys real plane capacitance.
2. HF caps in 0201 within 3 mm of the BGA pad. Beyond 3 mm, the trace inductance from cap to via wipes out the benefit.
3. Use via-in-pad on the HF caps where the fab allows it. Cuts the via-to-pad inductance roughly in half.
4. Avoid clustering all HF caps on one side of the BGA. Spread them around the periphery — the BGA is drawing current symmetrically and the return path is shorter when caps are local.

For Gen4+ SerDes lanes and DDR5, you'll find yourself targeting plane capacitance and package-level decoupling rather than discrete components. The discrete caps still matter; they just stop being the marginal lever.

PI simulation has a reputation for being expensive and slow. Done badly, it is. Done well, it pays for itself on the first programme that doesn't need a re-spin because of PDN problems. The trick is knowing when to run it and what to look at.

When we always simulate

• Any SoC programme with peak transients above 5A.
• Any board with DDR4-3200 or faster memory (data eye is PDN-sensitive).
• Any rail feeding a SerDes lane Gen3 or faster.
• Any design where the customer is in safety-critical (medical, automotive, aerospace) and the Z-target is tight.

When we skip the simulation

• Low-power IoT designs with peak transients under 1A and standard MLCC fan-out.
• Re-spins of a previously simulated and measured design where the only changes are mechanical.
• Programmes where the silicon vendor provides a validated PDN reference and the customer is following it tap for tap.

What the simulation actually delivers

1. Z vs frequency plot per rail, from DC to the relevant bandwidth. Plotted against the Z-target.
2. Cap-by-cap contribution map — which caps are doing meaningful work, which ones could be deleted, where the gaps in coverage are.
3. Anti-resonance scan — flags any impedance peaks above the target that result from cap-value combinations.
4. Sensitivity analysis — what happens to the impedance curve if a cap drops out (open joint), if temperature swings, if DC bias derating is worse than nominal.

The simulation typically saves us four to eight capacitors per rail relative to a "stamp 30 and hope" approach. On a 12-rail SoC, that's roughly 60–80 fewer parts on the board. The BOM saving alone usually pays for the simulation effort.

Simulation predicts. Measurement confirms. On any PDN we've taken seriously, we measure the real board against the simulated curve and adjust if the gap is meaningful. Three measurements are enough for most cases.

1. Bench-top impedance sweep (Bode 100 or equivalent)

A two-port VNA-style measurement from DC to 100 MHz, injected at a test point on the rail with a known calibration trace. Output is a measured Z vs frequency curve that we overlay on the simulation. Mismatches above ~5 dB are worth investigating — usually a missing cap, a placement that drifted from intent, or a plane that's narrower than the layout suggested.

2. Load transient response (programmable load)

Wire an electronic load to the rail and program it to step from 10% to 90% of peak current with a controlled slew. Measure rail voltage with a fast probe (≥500 MHz BW) in single-shot. The undershoot tells you about your bulk capacitance; the ringing tells you about your mid-frequency network; the steady-state recovery tells you about your bandwidth.

3. Spectrum of rail noise during real workload

Run the board under the actual application load — a stress test, a real workload — and capture rail noise on a spectrum analyser. This catches the case where the simulation modelled a flat current draw but the real silicon has spikes at very specific frequencies that the PDN happens to be weak at.

What we do with the data

• If Z is within 3 dB of target across the band, ship.
• If Z is 3–6 dB high in a narrow band, add caps targeted at that band's SRF. One revision.
• If Z is >6 dB high or wide-band high, structural problem — plane width, regulator placement, stackup dielectric. Re-architect that rail.

"A simulated PDN is a guess. A measured PDN is a contract. Customers who skip the measurement always come back six months later to ask why the field units are glitching." — Pioneer Horizon PI team

If you have a multi-rail SoC programme heading to bring-up and you'd like a PDN characterisation in our lab, share the rail map and the schematic. We typically turn a full PI report around in two weeks per board.