Controlled Impedance for DDR5 and PCIe Gen5 — The Stackup Math That Matters

Up to PCIe Gen3, ±10% on differential impedance gave you enough eye margin to survive a noisy real-world board. By Gen4, that ±10% started eating into your jitter budget. At Gen5 — 32 GT/s with the PAM-style equalisation budgets PCI-SIG hands you — ±10% is no longer a passing target. We hold ±7% on Gen4, and ±5% on Gen5 lanes from the BGA escape through the connector launch.

The same compression has happened on the DDR side. DDR3 at 1600 MT/s would forgive a lot. DDR4 at 3200 MT/s started rejecting boards where the data-group impedance drifted across the lane. DDR5 at 6400 MT/s and beyond is uncompromising — you need consistent geometry, consistent stackup, and a reference plane discipline that doesn't allow for plane splits, antipads acting as discontinuities, or signal hops between reference layers.

Where the margin actually goes

• Insertion loss budget at 16 GHz Nyquist for Gen5 leaves you roughly 28 dB total channel loss. A 1Ω mismatch on a 50Ω trace contributes ~0.04 dB of return loss penalty per discontinuity. Twenty discontinuities, and you've spent a whole decibel on impedance variation alone.
• Jitter budget at 32 GT/s allows roughly 12 ps total. A poorly controlled via stub adds 3–4 ps. You don't have margin for that on more than one or two transitions.
• Crosstalk couples through impedance discontinuities. Mismatch at one trace radiates into the neighbouring pair.

"At Gen5, every via is a project. You don't get to add them and hope." — Pioneer Horizon signal-integrity team

The practical consequence: we no longer treat impedance as a number to hit on average. We treat it as a profile across the trace, and the trace either holds the profile or it doesn't pass.

Differential impedance is set by trace width, trace spacing, dielectric height, and dielectric constant — in that order of sensitivity. Copy-pasting a width/spacing pair from a different stackup is the most reliable way to miss your target by 5–8Ω.

Starting geometry by application

• PCIe Gen4 (16 GT/s, 85Ω): 4.5 mil / 6 mil spacing on a 3.5 mil dielectric to closest reference, Dk ≈ 3.9. Hold ±7% across the lane.
• PCIe Gen5 (32 GT/s, 85Ω): 4.0 mil / 5 mil on a 3.2 mil dielectric, low-loss material (Dk ≈ 3.6, Df ≤ 0.005). Hold ±5%.
• DDR4 (3200 MT/s, 100Ω diff / 40Ω SE): data nets 5 mil / 9 mil, address/command 5 mil single-ended with 3W spacing minimum.
• DDR5 (6400 MT/s, 100Ω diff / 40Ω SE): data nets 4.5 mil / 8 mil with mid-bus inverted routing, address/command on a separate reference plane from data.
• USB 3.2 SuperSpeed (90Ω): 5 mil / 7 mil on 3.5 mil dielectric, hold ±10% — still forgiving relative to PCIe at the same rate.

The four geometry mistakes we see most

1. Spacing variation through BGA escape — pairs get squeezed past the via field and your impedance climbs 8–12Ω locally. Plan the escape route as a separate impedance segment.
2. Asymmetric pair routing — one trace runs under a plane edge, the other runs over solid copper. Common-mode conversion appears, EMC suffers.
3. Length matching by tromboning — adding serpentines to length-match the lanes locally narrows the differential coupling and shifts impedance. Use bent-pair length-tuning patterns, not loose serpentines.
4. Reference plane mismatch — pair routed above a power plane on layer L2 but its return path expected on the ground plane at L4. The return current detours; impedance spikes.

For a complementary view on how these geometry rules trade against routing density on DDR data groups, our crosstalk budgeting article goes into the spacing math.

If we had to identify a single failure mode that explains most of the impedance problems we see on customer boards at Gen3 and above, it would be undisciplined reference planes. The trace itself is rarely the problem. The return path is.

The principles we hold

• Every high-speed signal has a continuous reference plane on the immediately adjacent layer. No exceptions on SerDes, no exceptions on DDR data groups.
• The reference plane is solid copper across the entire trace footprint plus 3× the dielectric height on either side. Anything narrower lets return current squeeze and impedance drifts.
• Plane splits are forbidden under high-speed signals. If you must route a signal across a split (e.g., crossing from one power-domain reference to another), add stitching capacitors on both sides of the crossing, sized for the relevant frequency.
• Layer changes need return path planning. Going from L1 to L4 doesn't just mean a via for the signal — it means the return current also needs a path between the reference planes at L2 and L5. That's why ground stitching vias around signal-layer-change vias exist.

What goes wrong without it

Three real cases from our SI lab in the last 18 months:

1. USB 3.1 link training failure on a customer board — root cause was a 6mm section where the SuperSpeed pair crossed an antipad cluster on the reference plane. The plane was effectively absent. Impedance jumped to ~140Ω locally. Fix: relocate the antipad cluster, link came up clean.
2. DDR4 data group failing margin test at high temperature — root cause was a 1.5mm split under the address bus that wasn't visible on the routing layer. Fix: stitch the split with three 22nF caps; margins recovered.
3. PCIe Gen3 failing compliance at 8 GT/s — root cause was a single via with a 0.4mm stub through three layers of unused via barrel. Fix: back-drill from the bottom; eye opened immediately.

None of these required exotic test equipment to find. All three required a TDR sweep and a willingness to read the trace as a system, not as a line on a CAD layer.

The impedance target is set by the bus standard. The geometry is set by the stackup. The stackup is set by the material and the layer count. You can't choose the third variable independently of the first two and expect the numbers to land. Here's how we walk the decision tree for high-speed designs.

Dielectric material choice

1. Standard FR-4 (Dk ≈ 4.2 at 1 GHz, Df ≈ 0.018) — fine up to PCIe Gen2, marginal at Gen3, unacceptable at Gen4+. Loss tangent dominates above 5 GHz.
2. Mid-loss laminates (Dk ≈ 3.9, Df ≈ 0.010) — Isola FR408HR, Panasonic Megtron 4. Work cleanly through Gen3, holdable for short Gen4 channels under 6 inches.
3. Low-loss laminates (Dk ≈ 3.6, Df ≈ 0.005) — Megtron 6, Tachyon. Required for Gen4 at trace lengths above 8 inches and for any Gen5 design we accept.
4. Ultra-low-loss (Dk ≈ 3.3, Df ≈ 0.002) — Megtron 7, I-Tera. For Gen5+ on long channels or for 56G+ SerDes. Cost is significant; specify only when the budget requires it.

Layer count and assignment

• Signal layers should be adjacent to a solid reference plane on at least one side. This forces an even layer count for any board with high-speed content.
• Power planes are not reference planes for high-speed return. They look like one at DC. They are not one at GHz. Use ground planes for high-speed reference.
• Symmetric stackups minimise warpage during reflow. Asymmetric stackups (intentional or accidental) produce boards that bow, which messes with reflow paste deposition.

We typically deliver three stackup variants to a customer at the 20-minute DFM call: a cost-optimised, a performance-optimised, and a balanced option. The customer picks; we lock the impedance targets against the chosen stackup before any routing begins.

The impedance you simulated in the field solver and the impedance you measured on the panel are usually within ±2Ω. Sometimes they aren't. The only way to know which side of the line you're on is to measure. We measure every high-speed lot on coupons and on representative production traces, and we keep the data per panel.

What we measure

• TDR sweep on coupons — one coupon per panel, sampled. Tracks impedance vs position along the trace; flags discontinuities, stub lengths, and via effects.
• Insertion loss on representative traces — VNA sweep from DC to 20 GHz on production lots above Gen3. Compares against the predicted channel response.
• Return loss — same sweep, same coupon. We hold ≤-10 dB across the relevant Nyquist range for Gen3, ≤-12 dB for Gen4+.
• Cross-section — destructive, one board per lot, on first article and on any lot where electrical measurements drift. Validates the lamination matched the stackup drawing.

What the data has told us

Across roughly 2,400 high-speed lots over four years, the systematic biases we've documented:

1. Inner-layer trace widths run ~0.5 mil narrower than nominal due to etchback. Plan the field solver to compensate; expect impedance ~1.5Ω high on bare drawing widths.
2. Dielectric heights are repeatable within ±5% per lot for prepreg-only sections, but ±10% across vendor changes. Lock the vendor when impedance margins are tight.
3. Plating thickness on outer layers varies ±25% with current density across the panel. Outer-layer impedance accordingly shifts; we hold to a tighter tolerance only where the design demands it.

"Simulation tells you what the board should be. Measurement tells you what it is. The gap between those is your engineering margin." — Pioneer Horizon SI lead

If you're carrying a Gen4 or Gen5 design and would like a TDR/VNA characterisation before you commit to volume, send us the Gerbers and the impedance targets. We'll measure a five-board pilot and return a full SI report within two weeks.