Designing for IPC Class 3: The Five Rules That Most Designs Get Wrong

IPC Class 3 is not "Class 2, but stricter". It is a different design discipline applied to products where uninterrupted service is required and the field-failure cost is unbounded — medical implants, avionics, life-support systems, military electronics. The acceptance criteria in IPC-A-600 (bare board) and IPC-A-610 (assembly) are tighter, but the larger change is in the design rules that have to be in place upstream so that those acceptance criteria can be met.

A board designed to Class 2 rules and built to Class 3 inspection acceptance will fail. Not always at FAI, sometimes not until ramp, but it will fail. The single most common audit finding we see when a customer arrives with a "Class 3 design" that was actually drawn against Class 2 rules: annular ring on inner layers below the Class 3 minimum, on hundreds of vias, in a way that can't be patched at the fab level.

The numerical differences that matter most

• Annular ring, inner layer — Class 2: 0.05mm minimum; Class 3: 0.075mm minimum (after registration tolerance is consumed).
• Annular ring, external layer — Class 2: 0.05mm; Class 3: 0.075mm.
• Solder mask sliver between pads — Class 2: 0.05mm acceptable with documentation; Class 3: 0.10mm minimum, no exception.
• Conductor width reduction (etch-back, nicks) — Class 2: up to 30% allowed; Class 3: up to 20%.
• Conductor spacing reduction — Class 2: 30%; Class 3: 20%.
• Plated-through-hole copper plating — Class 2: 20µm; Class 3: 25µm.
• Wicking distance (into glass strands) — Class 2: 125µm; Class 3: 80µm.

"Class 3 is not a stamp you apply at FAI. It's a constraint set you apply at CAD. By the time the board is in the inspector's hand, the design is either Class 3 or it isn't — and no amount of careful manufacturing recovers the difference." — Pioneer Horizon quality lead

The five rules that follow are the ones we see designs miss most often. They are not the only Class 3 rules; they are the ones whose absence produces the most expensive findings during audit or first-article inspection.

Annular ring is the copper that remains around a drilled hole after fabrication. The minimum is dictated by the inspector's measurement — but the design has to anticipate that measurement, because what you draw in CAD is not what survives fab-side registration tolerance.

The arithmetic

Annular ring at the inspector's measurement = (Pad diameter − Hole diameter) / 2 − Registration tolerance.

For Class 3 on an inner layer, the inspector needs to see at least 0.075mm of copper per side. Registration tolerance at a standard fab is 0.075mm; at a tight-tolerance fab, 0.050mm. Working backward:

• Class 3, standard fab: pad diameter ≥ hole diameter + 2 × (0.075mm + 0.075mm) = hole + 0.30mm.
• Class 3, tight-tolerance fab: pad diameter ≥ hole diameter + 2 × (0.075mm + 0.050mm) = hole + 0.25mm.
• Class 2 equivalent: pad diameter ≥ hole + 0.20mm at standard, hole + 0.15mm at tight.

The Class 2 design imported into Class 3

This is the audit-killer. A board originally drawn for Class 2 typically has via-pad-to-hole at hole + 0.20mm. Imported into Class 3 fabrication, every inner-layer via is borderline — half the production lot will measure at or below the 0.075mm threshold, and inspector judgement on a sample becomes the rejection criterion. The fix is not "ask the fab to register more accurately"; it's grow the pads by 0.10mm at CAD and re-do the design rule check.

The CAD rules we set on every Class 3 design

1. Default via pad: hole + 0.30mm (e.g., 0.30mm drill → 0.60mm pad; 0.20mm drill → 0.50mm pad).
2. Microvia laser-drilled blind: hole + 0.20mm (tighter registration on microvias allows this).
3. Component-pin PTH: hole + 0.40mm to leave headroom for the larger registration tolerance on plated-through component holes.
4. Tooling holes: minimum 1.0mm clearance to nearest copper; tooling holes are not subject to Class 3 annular but they consume real estate that the design needs to account for.

Run a CAD-side DRC against these widths after every layout pass. The cost of growing the pads at CAD is zero; the cost of finding the violation at FAI is a board re-spin.

Class 3 mask requirements look like Class 2 with smaller numbers, but the working consequence is larger: the mask process cannot produce a feature smaller than its own tooling resolution, and an inspector at Class 3 will reject what an inspector at Class 2 would document with a deviation.

The solder-mask sliver problem

Between two adjacent SMD pads, the mask "sliver" — the strip of mask material between them — has a minimum width below which the mask manufacturer will either skip it (leaving bare copper) or print it and have it lift off during reflow.

• Class 2 minimum sliver: 0.05mm; below that, fab is allowed to gang-mask (open both pads as one window).
• Class 3 minimum sliver: 0.10mm, with no gang-masking exception. Below 0.10mm and the board is not Class 3.

What this drives at CAD

• 0402 packages on 0.5mm pitch: pad-to-pad mask sliver is roughly 0.10mm at the standard footprint. Class 3 requires the package vendor's "tight" or "Class 3" footprint variant, which widens the gap to 0.13mm. Use the Class 3 footprint by default.
• QFN exposed-pad designs: between the centre exposed pad and the perimeter leads, mask sliver often shrinks below 0.10mm. The fix is mask-defined pads on the perimeter (mask opening 0.075mm inside the copper pad edge) to widen the sliver.
• BGA via-in-pad: type-3 via fill (epoxy-filled + plated over) is required for Class 3 on any via inside a BGA pad. Tented via on a BGA pad is a non-starter.

Silkscreen rules that get missed

1. No silk on pads — Class 3 inspectors measure mask edge of pad to nearest silk edge; minimum is 0.15mm.
2. Silk linewidth minimum 0.15mm (6mil) — below that, the silk doesn't reliably print and reference designators become unreadable.
3. Silk character height minimum 1.0mm for primary reference designators, 0.8mm for polarity marks. Class 3 requires legibility under 3× magnification.
4. Polarity indicators on every polarised component, on every assembly drawing layer, with no overlap to other silk.

The silk rules are the most common "small" finding at Class 3 FAI — every Class 3 audit we've seen has caught at least one violation here. They're cheap to fix in CAD; expensive to argue about at FAI.

Plated-through-hole copper plating is the structural element of multilayer connectivity. Class 3 specifies a minimum of 25µm of copper plating in the barrel — measured at the thinnest point of a microsection — and this number cascades into both fab process control and design choices around aspect ratio.

The fab-process variables

Plating thickness in a barrel depends on:

• Aspect ratio (hole depth ÷ hole diameter). Above 8:1, electroplating uniformity drops; above 10:1, only a Class 2 fab can reliably hold 20µm, and Class 3 25µm is at the edge of capability.
• Acid copper bath chemistry — additives, leveler concentration, throwing power. Class 3 fabs run tighter chemistry control with daily titration.
• Pulse-plating vs. DC plating — pulse-plating gives better barrel-to-surface ratio for high aspect ratios. Most Class 3 production today uses pulse.

What the design has to do to make Class 3 plating achievable

1. Keep aspect ratios sane — design target 8:1 or below. A 1.6mm board with 0.20mm vias is 8:1 — fine. A 2.4mm board with 0.20mm vias is 12:1 — not Class 3 reliable.
2. Use microvias for inner-layer connectivity on high-density designs — sequential lamination with laser-drilled microvias avoids the high-aspect-ratio plating problem entirely.
3. Avoid via-in-pad on through-vias for SMD parts — through-via in BGA pad without filling traps solder during reflow. Class 3 requires type-3 via fill (epoxy-filled, copper-capped, planarised).
4. Specify the via class in the fab notes — "Vias to be plated per IPC-6012 Class 3, 25µm minimum barrel copper, microsection coupon attached to every panel."

The blind-and-buried decision

For HDI boards (high density interconnect), blind and buried vias are not optional for Class 3 — they're often required to keep aspect ratios in the achievable range. The cost adder is roughly 30–60% per additional sequential lamination cycle, but the alternative (mechanical through-vias in a 6-mil drill into a 3mm board) is not Class 3 producible at scale.

For a deeper walk-through of how stackup and via choices interact, our PCB design handbook covers the upstream stackup decisions that decide whether your Class 3 fab quote is reasonable or absurd.

The last two rules are where Class 3 design discipline meets Class 3 production discipline. They are not strictly CAD-side rules — they are constraints the design has to be aware of so the production process can satisfy them.

Rule 4 — Conformal coating coverage and thickness

Class 3 conformal coating per IPC-A-610 Class 3 (and the matching IPC-CC-830 material standard) requires:

• Coverage — every electrically-functional surface coated; explicit keep-out zones (test points, connectors, programmable headers) called out on a coating drawing.
• Thickness — 25–75µm for AR (acrylic) and UR (urethane) classes; 50–210µm for SR (silicone). Measured by wet-film gauge or non-destructive thickness gauge on coupons.
• No bridging across high-voltage isolation boundaries — coating that crosses an isolation barrier reduces the effective creepage, defeating the design.
• No bubbling, no orange-peel, no debonding — visible defects under 4× magnification reject the panel.

The design implication: every Class 3 design needs a coating drawing as a deliverable separate from the assembly drawing. Test points, connector recesses, programming pads, debug headers, and any heat-sensitive component (e.g., crystals) need keep-out callouts. The coating drawing is reviewed by both fab and customer at FAI.

Rule 5 — Per-board traceability through every process step

Class 3 builds for any regulated industry (medical, aerospace, defence) require traceability from raw material to deployed serial number. Every panel, every assembly, every component lot, every operator, every test result — bound to the unit's serial via the MES.

• Raw board lot — fab lot number traced through SMT, including impedance-coupon and microsection results.
• Solder paste batch — lot, exposure-out-of-jar time, viscosity result at line-side check.
• Component lots — every reel, every tube, every tray, with date code and supplier traced to the serial.
• Reflow profile — actual measured profile (KIC/SolderStar trace) at the panel's exact position on the conveyor, archived per panel.
• Test results — every measurement attached as raw data, not summary.
• Operator — every workstation, every signature, every certification check.

"Class 3 doesn't end at the bare board. It threads through every step the board ever passes — and the traceability has to support an audit five years after the unit shipped." — Pioneer Horizon quality lead

For the working traceability model — including how solder paste batches and operator IDs get bound to each serial — see our per-board traceability article. The design implications: every assembly needs a permanent serial mark (laser-engraved into a board-edge keep-out, or DPM 2D code on a no-component zone), and that serial has to be readable by the line's vision system at every station.

If you're moving a Class 2 design to Class 3 fabrication for an upcoming regulated programme, send us the CAD package and we'll redline it against the five rules above. The redline typically catches 80–120 design-level findings — every one of which would have been an FAI rejection had the design gone to fab unchanged.