Why voids cluster under thermal pads, the X-ray signatures that distinguish process from design causes, and the reflow tweaks that actually move the needle.
Visual inspection passes, AOI passes, and your boards still fail at customer site. A walk-through of how reflow ramp rates and peak temperature drift produce hidden weakness.
The mechanical reality of running 0201 components at production speed, and the layout decisions (paste apertures, pad geometry, courtyard spacing) that make it possible.
The economic and reliability case for rework vs. replacement on $40 SoCs and $400 FPGAs, and the rework profile we use to keep void rates under 8%.
When mixed-tech boards benefit from selective wave, when intrusive reflow is cheaper, and how the choice cascades into BOM and DFM decisions upstream.
Refrigeration logs, room-temperature conditioning windows, and the humidity controls that explain why winter-build yields beat monsoon-build yields by 1.4%.
Algorithm thresholds, lighting profiles, and the regression dataset we maintain to keep the AOI catching real defects without burying the line in false positives.
The reduction percentages we use for fine-pitch packages on the same board as 0201s, with the rationale for each (paste volume, slumping, head-in-pillow risk).
At what THT-component count does selective wave beat hand-soldering on labour cost, and what does it mean for your CAD courtyards and panelisation?
Cost, reworkability, dielectric withstand, and chemical resistance compared head-to-head across the three coating families we routinely apply.
Hot-air, infrared, and convection profiles indexed by package size, ball pitch, and substrate thickness — with the thermocouple placements we use to validate them.
The volume threshold at which an ICT fixture pays back its tooling cost vs flying-probe, and how DFT decisions in CAD move that threshold.