ICT Fixture Cost vs Test Coverage — When the Bed-of-Nails Earns Its Keep

The choice between in-circuit test (ICT) on a custom bed-of-nails fixture and flying-probe test (FPT) on a generic platform is a unit-economics question, not a quality question. Both deliver high test coverage when done well. They differ on tooling cost, per-board cycle time, and how those two variables interact with your production volume.

The simple breakdown:

• ICT fixture cost — $8,000 to $30,000 for a typical SMT-only board, depending on pin count and complexity. Single-sided fixtures sit at the low end; clamshell dual-sided fixtures with 1,200+ pins sit at the top.
• ICT cycle time — 30 to 90 seconds per board, depending on test list length. Setup between board types is roughly 5 minutes.
• FPT cycle time — 6 to 18 minutes per board, depending on net count and probe placement. No fixture, so setup is software-only.
• Test programme development — 3–5 days of engineering time for ICT, 1–2 days for FPT.

"Below 800 units a year, flying probe wins on every metric that matters. Above 4,000 units a year, the ICT fixture has paid itself off twice. The interesting question is what to do in the middle." — Pioneer Horizon test lead

This article walks the break-even math, the DFT decisions that move it, and the hybrid strategies we use for customers in the volume range where neither pure answer fits.

Let's run real numbers for a representative board: 320 net count, 95 ICT test points, 600 components, moderate complexity. Assume our labour rate fully loaded at $35/hour and our equipment-amortisation rate at $25/hour for the FPT system, $20/hour for the ICT system after fixture amortisation.

FPT per-board cost

• Cycle time: 11 minutes per board.
• Per-board cost at full machine utilisation: ($35 + $25) × (11/60) = $11.00.
• No fixture amortisation — programme development is one-time and small.

ICT per-board cost (with $15,000 fixture)

• Cycle time: 45 seconds per board.
• Per-board cost at full machine utilisation: ($35 + $20) × (0.75/60) = $0.69.
• Fixture amortisation: $15,000 ÷ programme lifetime volume.

Break-even volume

Solve for the volume V where total ICT cost = total FPT cost:

• $0.69 × V + $15,000 = $11.00 × V
• $10.31 × V = $15,000
• V ≈ 1,455 units

For this representative board, ICT pays back the fixture investment at roughly 1,500 units of production. Below that volume, FPT is cheaper. Above it, ICT is cheaper — and the gap grows fast: at 10,000 units, the ICT cost advantage is over $100,000.

The math shifts with fixture cost (more pins, dual-sided) and per-board cycle time. For a 1,200-pin clamshell fixture at $30,000, the break-even pushes to roughly 2,900 units. For a simple 200-pin fixture at $8,000, it drops to about 780 units.

The break-even volume isn't fixed by the board — it's fixed by the test programme the board supports. Two CAD-level decisions change the math materially. We push customers to make both before layout starts because retrofitting them on a finished board costs significantly more than designing them in.

Test point density

Every net you can probe with ICT contributes test coverage. Every net you can't probe is either an FPT-only net or an untested net. The standard rule is one test point per net for power and ground, and one test point per signal net where the topology permits.

• Test point size — 1mm diameter pad is generous, 0.7mm is workable, below 0.5mm risks probe failure and fixture wear.
• Test point spacing — minimum 2.54mm centre-to-centre prevents probe collision and simplifies fixture build.
• Test point clearance — 0.5mm minimum from any tall component. Probes need vertical access.

Boundary scan (JTAG) coverage

Where ICT pin count drives fixture cost, JTAG boundary scan reduces that pin count. A board with comprehensive JTAG can drop ICT pin count by 30–50% by replacing physical probing of internal nets with boundary-scan vectors. JTAG TAP access plus a handful of strategic ICT pins yields fault coverage comparable to a much larger ICT-only programme — at a fraction of the fixture cost.

What we ask for at DFM review

1. Net list with test-point coverage marked. Anything below 90% triggers a review.
2. JTAG chain documentation if any device on the board supports it.
3. Power-rail control points — every rail that can be independently powered down for safe ICT access.

For deeper DFM coverage of layout decisions that affect downstream cost, our PCB design handbook walks the same review at the stackup/impedance level.

Most of our customer programmes live in the 1,000–5,000 units-per-year band. Neither pure ICT nor pure FPT is optimal for the whole programme. We use four hybrid approaches that bend the math in customer-specific ways.

1. FPT for prototype + early production, ICT for sustained production

Build a flying-probe programme for the EVT through PVT phase. Only commission an ICT fixture once the board design is locked and the volume forecast is firm. This pushes fixture investment to the point where the cost is justified, and protects against fixture being scrapped due to late design changes.

2. ICT for the high-coverage subset, JTAG for the rest

Design a low-pin-count ICT fixture (300–500 pins) that probes power rails, critical analog nets, and boundary-scan entry points. Use JTAG to cover the rest of the digital fabric. Fixture cost stays under $10,000 even on complex boards; programme break-even drops to 600–800 units.

3. ICT for production, FPT for failure analysis

Production runs on the fixture. Boards that fail ICT and need deeper diagnostic don't queue up at the fixture — they go to the flying probe, where engineering can probe arbitrary nets without modifying the fixture. This keeps the production line moving while engineering chases the root cause offline.

4. Shared-fixture programmes

Some product families share enough common nets that one fixture can serve multiple board revisions. Spending an extra $4,000 on the fixture to support two future revisions is cheaper than two separate fixtures.

• Approach 1 fits most customer programmes through their first year of production.
• Approach 2 is our standard recommendation for any board with substantial JTAG coverage.
• Approach 3 is the production-grade pattern we use on customer programmes with strict line cadence.
• Approach 4 requires upfront planning across the product family and is rarer in practice.

The economic model behind each approach is documented per-customer in the test plan that ships with the first NPI build. The plan is revisited at each annual programme review against the latest volume forecast.

Test coverage is a contested metric. There are three common definitions and they don't agree with each other:

• Node coverage — fraction of nets that have at least one test point. Easy to measure, often the headline number on a test plan.
• Component coverage — fraction of components whose presence/orientation can be verified. Lower than node coverage on dense boards.
• Fault coverage — fraction of plausible defect modes (open, short, wrong value, wrong polarity) that the test catches. Harder to compute, but the only metric that matters at the line.

Real numbers from our line

Across customer programmes audited in the last year, the typical numbers we hit are:

• Pure FPT — node coverage 94–98%, component coverage 88–94%, fault coverage 82–90%.
• Pure ICT — node coverage 90–95% (limited by test-point density in CAD), component coverage 92–97%, fault coverage 88–94%.
• ICT + JTAG + functional test — combined fault coverage 96–99%, the highest production-grade coverage we routinely achieve.

What the tests actually catch

1. Shorts — both ICT and FPT catch them at near-100%. The difference is cycle time.
2. Opens — ICT marginally better on edge cases (intermittent solder joints under reflow).
3. Wrong-value passives — ICT clearly better, especially for 1% tolerance discrimination on smaller passives.
4. Component orientation — both adequate when paired with AOI upstream.
5. Live-circuit functional faults — neither ICT nor FPT alone catches these reliably; functional test or system-level test is the only credible answer.

If you're sizing up an ICT investment for an upcoming programme, the question we ask first is "what's your three-year volume forecast and what's your AOI false-call rate today?" Those two numbers and the BOM tell us whether the fixture makes sense. Share the BOM and forecast and we'll come back with a recommended test strategy and a cost model inside a working week. For the AOI side of the line, our AOI false-fail tuning article covers the upstream coverage discussion.