DC-DC Converter Boards for Solar Inverters — IGBT Layout and Snubber Selection

Solar inverter DC-DC stages and the H-bridge or three-phase inverter sections downstream of them are dominated, electrically, by a single number: the parasitic inductance of the commutation loop around each IGBT. At a 1000V bus and 20kHz switching with di/dt in the 1–3 kA/µs range, even 30 nH of stray loop inductance produces a 30–90V overshoot on every turn-off. That overshoot stacks on top of the bus voltage and the IGBT collector-emitter rating; exceed the rating and the part either avalanches into clamp every cycle (degrading reliability) or fails outright into a short that drops the inverter.

What sets the loop inductance

• Physical area of the loop — the rectangle formed by the bus capacitor, the upper IGBT, the load path, the lower IGBT, and the return to the cap. Inductance scales roughly with enclosed area.
• Geometry of the bus structure — wide flat copper running close together has much lower inductance than thin traces spaced apart.
• Capacitor type and termination — film caps with low-ESL terminations dominate, but the lead length from the cap can to the IGBT package matters as much as the cap itself.

"On a 30 kW inverter we measured 47 nH of total loop inductance on the first prototype. The IGBT was rated 1200V and the bus was 800V. Switching transients touched 1150V at full load. We respun the bus-bar plane and got loop inductance down to 18 nH — overshoot dropped to 920V, snubbers shrank, and operating temperature on the IGBTs fell 11 °C." — Pioneer Horizon power electronics engineer

The work below covers what we have learned about driving that number down on real customer boards, and what trade-offs the layout decisions force on the rest of the design.

The single most effective lever for loop inductance is geometry. Two principles dominate: minimise the enclosed area of the commutation loop, and place the forward and return currents close together so their fields cancel. On a multi-kW inverter, that usually means a laminated bus bar above the IGBTs and a tight PCB structure connecting the gate drive and the snubbers.

Laminated bus-bar construction

• Copper-insulation-copper sandwich, with the positive bus on one plate and the negative bus on the other, separated by 0.2–0.5 mm of insulating film.
• The two plates run parallel for the full length of the bus, including over the capacitor banks and up to the IGBT terminals.
• Capacitor connections drop from the bus plates directly down to the cap terminals — no long leads.
• IGBT connections from the bus plates land on the IGBT collector and emitter terminals through short tabs.

A well-designed laminated bus bar typically delivers 8–20 nH of total loop inductance for a half-bridge module. Compare that to a wired bus that runs 60–150 nH, and the case for the bus bar is the case for the inverter working at all.

When PCB-only construction is viable

For smaller inverters — say below 5 kW — a multi-layer PCB with thick copper planes can substitute for the laminated bus bar. We use 2 oz or 3 oz copper, with the positive and negative bus planes adjacent on layers 2 and 3 of a 6-layer board, separated by a single dielectric. The geometry gives roughly the same field cancellation as a laminated bus bar, at the cost of current capacity. Above 100 A continuous, the PCB starts to run hot and the bus-bar approach becomes mandatory.

Where the loop area sneaks back in

• Long DC-bus capacitor leads — even with a good bus structure, 20 mm of cap lead can add 15 nH.
• Asymmetric current paths around the bus — make sure the forward and return paths overlap, not run side by side.
• Power module pinout — some packages force a loop area that no external geometry can fully recover.

Field cancellation is binary: either the geometry forces it or it does not. The measurement on the prototype is the only thing that tells you whether you got it right.

The gate drive of an IGBT in a high-side or floating position has to be isolated from the controller side. At 800V bus and 1 kA/µs switching, the floating gate driver's reference is moving relative to ground at 1 kV/µs during transitions — and any isolation barrier between the controller and the gate driver has to survive that common-mode transient without coupling noise back to the controller or causing the driver itself to glitch.

Isolation technology choices

• Optocouplers — traditional, cheap, but slow and prone to common-mode transient immunity (CMTI) issues at high dV/dt. Modern high-CMTI optos are rated to 50 kV/µs; older ones fail at 5–10 kV/µs.
• Capacitive-isolation digital isolators — fast, high CMTI (often 100+ kV/µs), with integrated gate drivers in some parts. The default choice on new designs.
• Magnetic isolation — pulse transformers and coreless transformer ICs. Excellent performance, slightly higher cost, often the right answer for the highest dV/dt designs.

Isolation barrier layout

The isolation barrier on the PCB has to honour both creepage and clearance for the working voltage of the bus, and the barrier carries through the inner layers of the stackup. For a 1000V bus, we hold 8 mm minimum creepage and 5 mm minimum clearance, with inner-layer copper kept off the barrier path. Where mounting holes or test points cross the barrier, we cut slots in the FR-4 to break the surface creepage path entirely — the same technique used for medical isolation, scaled to higher voltage. For the medical-side context see our IEC 60601-1 article; the geometry rules are similar at lower voltage.

Gate resistor and turn-on/turn-off shaping

• Separate turn-on and turn-off gate resistors, allowing independent control of dI/dt and dV/dt at each transition.
• Turn-on resistor sized to manage diode reverse-recovery current in the opposite leg — typically 5–15 Ω for a 100 A IGBT.
• Turn-off resistor sized to keep transient over-voltage within the IGBT envelope — typically 10–30 Ω, sometimes with active clamping.
• Anti-parallel diode from gate to emitter to provide a fast turn-off path independent of the driver pulldown.

The gate-drive layout is the second most common cause of inverter failure we see, after loop inductance. A clean isolation barrier and a deliberate gate-drive layout pay back the engineering time many times over.

Snubbers absorb the residual energy in the parasitic loop inductance that the bus geometry could not eliminate. A good snubber is small, low-loss, and tuned to the actual ringing frequency of the loop. A bad snubber either does nothing or burns enough power to need its own heatsink. The three families we use on solar inverter work are RC snubbers, RCD snubbers, and active clamping.

RC snubber

A series resistor and capacitor placed directly across the IGBT collector-emitter, sized to damp the ringing of the parasitic loop inductance with the IGBT output capacitance. Sizing rules:

• Capacitor value chosen so its impedance at the ringing frequency matches the characteristic impedance of the loop — typically 10–47 nF.
• Resistor value chosen for a damping factor of about 0.5 at the ringing frequency — usually 5–22 Ω for the parts we work with.
• Resistor power dissipation calculated for the actual switching frequency and bus voltage; size for 3× margin.

Use an RC snubber when ringing is moderate and the energy per cycle is small. They are simple, predictable, and they fit on the PCB.

RCD snubber

Adds a diode in the snubber loop to clamp only the over-voltage portion of the ring, recycling the rest of the energy back to the bus through a separate path. RCD snubbers are more efficient than RC at higher power and let you handle larger over-voltages without growing the resistor dissipation.

Active clamping

An active clamp uses a TVS or a controlled MOSFET between the IGBT collector and gate to deliberately limit the peak collector voltage. It is the most efficient option for hard-switched inverters above 30 kW. The cost is a more complex gate-drive circuit and additional control discipline.

Measured ringing before and after

On a recent 50 kW PV inverter we measured the half-bridge ringing before snubber: peak collector voltage 1085V on an 800V bus, ringing at 32 MHz, damping factor 0.06. After tuning a 22 nF / 10 Ω RC snubber: peak 905V, damping factor 0.42. The IGBT junction temperature at full load dropped 7 °C, and the EMI signature at 32 MHz dropped 18 dB. The change cost two component placements and three weeks of qualification testing — paid back inside the first qualification month against the redesign that would otherwise have been required.

Every IGBT-stage design decision sits at the intersection of three concerns: switching loss (driven by transition speed), conduction loss (driven by current and on-state voltage), and electromagnetic emissions (driven by transition speed and loop geometry). You cannot optimise all three independently. The job is to find a working point where the inverter is efficient, reliable, and compliant, without paying the full cost of any one metric.

The trade-off triangle

• Fast switching — reduces switching losses, allows higher operating frequency, gives better current control bandwidth. But: higher EMI, higher over-voltage transients, more demand on isolation and snubbers.
• Slow switching — reduces EMI, eases the gate-drive design, relaxes snubber sizing. But: higher switching losses, lower efficiency, lower bandwidth.
• Lower bus voltage — reduces transient stress and EMI. But: higher current for the same power, more conduction loss, larger conductors.

Where we typically settle for solar inverter work

For 10–50 kW string inverters running 600–1100V bus and 16–20 kHz switching, the working point usually falls in this band: gate resistors tuned for dV/dt around 5 kV/µs, loop inductance under 25 nH, snubber selected to clamp over-voltage to 80% of IGBT rating, conducted EMI margined 6 dB below the CISPR-11 Class A limit. That working point is the result of converged iteration on six or seven prototypes per platform.

Thermal path discipline

• Direct-bond copper baseplate or thermal via array under any power module, with metric-screw thermal connection to the heatsink.
• Thermal pad selection — ceramic-filled silicone for general use, phase-change material for the highest performance.
• Temperature measurement on every IGBT module, fed back to the controller for derating under load.
• Conformal coating compatibility with the thermal interface — many coatings will not stick to silicone pads, leaving an edge gap that defeats the coating's intent.

EMI considerations on the PCB

Common-mode currents from the high-dV/dt switching nodes couple into chassis ground, cable shields, and adjacent boards. We routinely add common-mode chokes on the AC output, a chassis-ground star point underneath each phase leg, and shielded gate-drive transformer placement away from controller-side analogue circuitry. The pre-compliance scan on the EMC chamber is where the layout pays off or does not; we typically run pre-compliance at our facility before sending the inverter to formal EMC test.

For deeper power-integrity discussion that complements the IGBT layout work, our team is glad to walk through customer schematics directly — share the bus topology and IGBT module choice and we will come back with a layout review and a loop-inductance estimate within five working days.